The present invention relates generally to high speed data transmission and conversion systems. The present invention relates more particularly to a Fibre Channel host bus adapter having a multi-frequency clock buffer which facilitates conversion of asynchronous serial data into clock aligned, framed, parallel data in a manner which reduces power consumption by driving selected portions of a serial to parallel data converter at reduced clock speeds.
High speed data transmission systems for communicating data between a computer and its associated peripherals, as well as between computers themselves, are well known. One example of such a high speed data communication system is Fibre Channel, which provides data transmission rates up to approximately 1 GHz when used with an optical fibre or coaxial cable transmission medium. When an optical fibre transmission medium is used, a Fibre Channel data transmission system can transmit data at such speeds even when the sender and receiver are separated by relatively great distances.
Data is transmitted over the optical fibre of a Fibre Channel system according to an asynchronous serial data transmission protocol. However, as those skilled in the art will appreciate, the internal architecture of contemporary computers is based upon parallel, byte-multiple signal buses (typically 8-bit, 16-bit or 32-bit buses). Thus, it is necessary to convert between the asynchronous serial data used for Fibre Channel communications and the parallel data used internally by the computer.
In a Fibre Channel system, byte-multiple parallel data must be converted by the transmitter into a 1 GHz asynchronous serial data signal for transmission along an optical fibre or coaxial cable and must be converted by the receiver from 1 GHz asynchronous serial data back into byte-multiple parallel data for internal use by a computer or peripheral.
In accordance with the Fibre Channel physical and signaling interface specification, defined in ANSI X3.230-1994, information to be transmitted over an optical fibre or wire cable is encoded, 8-bits at a time, into a 10-bit Transmission Character which is subsequently serially transmitted by bit. The data provided over a typical computer system parallel architecture is encoded and framed such that each data byte (8-bits from the point of view of the computer system) is formed into a Transmission Character in accordance with the Fibre Channel 8B/10B Transmission Code. The resulting 8B/10B Character is then transmitted as 10 sequential bits at approximately a 1 GHz data rate in accordance with the interface specification. Likewise, an incoming 8B/10B encoded Transmission Character must be serially received at an approximately 1 GHz data rate and converted (framed) into the corresponding 10-bit Transmission Character. The 10-bit Transmission Character is then further decoded into an 8-bit byte which is recognizable by such conventional computer architectures.
According to contemporary methodology, the conversion of high speed, e.g., 1 GHz, asynchronous serial data into byte-multiple data suitable for internal processing by a contemporary computer is performed by receiving the asynchronous serial data into a deserializer which comprises a serial in, parallel out shift register. The serial in, parallel out shift register is typically large enough-to capture an entire byte-multiple word of data, so as to facilitate the detection of a delimiter character, i.e., a character such as a comma which facilitates the proper framing of the data as byte-multiple parallel data words. The serial in, parallel out shift register must also be large enough to accommodate the byte-multiple data words themselves (which are typically of the same length as the delimiter character).
A pattern detection circuit facilitates identification and location of the delimiter character within the serial in, parallel out shift register and a word alignment circuit effects alignment of the framed delimiter and subsequent data words to a desired clock signal, e.g., a 100 MHz clock.
However, one problem commonly associated with such contemporary, high speed, serial to parallel data converters is the undesirably high power consumption associated therewith. A typical contemporary serial to parallel data converter suitable for converting approximately 1 GHz asynchronous serial data into 10-bit, 100 MHz parallel data comprises approximately 50 flip flops, of which approximately 40 are clocked at 1 GHz. Of course, each of these flip flops consumes electrical power and also contributes to the heat load of any integrated circuit of which it forms a part. Further, the clock driver required to drive the flip flops has to provide sufficient power to accommodate the fanout associated therewith.
The power consumption of such a contemporary, high speed, serial to parallel data converter is higher than desired because many of the flip flops thereof must be clocked at 1 GHz, thereby undesirably increasing power consumption, as discussed further below. One contemporary high speed serial to parallel data converter which utilizes fully synchronous design techniques is known to have a worst case power consumption of approximately 500 mW.
As those skilled in the art will appreciate, the heat dissipation of a circuit is directly proportional to the power consumed thereby. When a circuit is embodied in an integrated circuit chip, then it is particularly important to mitigate the heat dissipation thereof, so as to minimize the circuit""s contribution to the total heat load of the integrated circuit chip. The total heat loading of an integrated circuit must be maintained below a predetermined level so that the heat can be extracted from the integrated circuit chip (such as by using a heat sink, fan, or thermoelectric cooler, if necessary). If the heat generated by an integrated circuit chip cannot be removed therefrom fast enough, then the temperature of the integrated circuit chip increases and the integrated circuit chip is subject to malfunction and/or premature failure. Since every individual circuit of an integrated chip contributes to the heat loading thereof, it is desirable to minimize the heat load contribution of each individual circuit, so as to reduce the heat loading of the entire integrated circuit chip.
It is well known that the power consumption of a circuit is directly proportional to the frequency at which the flip flops thereof operate, according to the formula: power=capacitancexc3x97frequencyxc3x97voltage2. Thus, it is clear that reducing the frequency, i.e., clock rate, of selected flip flops by half reduces the power required to operate the selected flip flops by half as well.
In view of the foregoing, it is desirable to provide a serial to parallel data converter which operates with a substantial number of the flip flops thereof being clocked at a reduced rate, so as to mitigate power consumption and heat dissipation thereof.
The present invention specifically addresses and alleviates the above-mentioned deficiencies associated with the prior art by providing a serial to parallel data converter which has reduced power requirements. Reduced power consumption is facilitated by the use of an array of parallel registers for pattern detection which are clocked at a lower rate than the serial register of contemporary serial to parallel converters and therefore consume substantially less power than the contemporary serial register.
More particularly, the present invention comprises a Fibre Channel host bus adapter having a low power, high speed, serial to parallel data converter for converting asynchronous serial data into clock aligned, framed, parallel data. The data converter of the present invention comprises a serial in, parallel out register for receiving asynchronous serial data and for providing unframed parallel data. An array of parallel in, parallel out registers is configured to receive the unframed parallel data from the serial in, parallel out register and to move the received data in a parallel fashion between the parallel in, parallel out registers of the array.
A pattern detection circuit identifies the location of a delimiter character, e.g., a comma, within the array of parallel in, parallel out registers. A selection circuit reads desired data bits from the array of parallel in, parallel out registers in a parallel fashion, based upon the location of the delimiter character, so as to define a framed parallel output word containing either the delimiter character or a subsequent data word. A data alignment circuit aligns the framed parallel output word with respect to a desired clock, so as to define a clock aligned, framed parallel output word. Some data alignment may optionally be performed by the selection circuit, as well.
According to the present invention, the number of flip flops which are clocked at 1 GHz is substantially reduced as compared to contemporary high speed serial to parallel data converters. Reducing the speed at which the flip flops are clocked proportionally reduces the power consumption and heat dissipation thereof. The data converter of the present invention further comprises a multi-frequency clock. The multi-frequency clock comprises a first clock output port for providing a first clock signal to the serial in, parallel out register. The multi-frequency clock further comprises a second clock output port for providing a second clock signal to the array of parallel in, parallel out registers and to the detection circuit. The multi-frequency clock further comprises a third clock output port for providing a third clock signal to the data alignment circuit. The rate of the first clock signal is greater than the rate of the second clock signal and the rate of the second clock signal is greater than the rate of the third clock signal.
As those skilled in the art will appreciate, a 1 GHz clock signal is necessary to facilitate operation of the serial in, parallel out register when receiving asynchronous serial data at a rate of 1 GHz. However, since the serial in, parallel out register provides parallel data output at one fifth of the rate at which asynchronous serial data is input thereto, the array of parallel in, parallel out registers can be clocked at a rate lower than 1 GHz, e.g., 500 MHz. The final output of the serial to parallel data converter of the present invention is at 100 MHz, thus facilitating operation of the data alignment circuit at 100 MHz.
According to the present invention, a progression of slower clock signals is provided from the input of the serial to parallel data converter to the output thereof. In this manner, the frequency of selected portions of the serial to parallel converter is substantially reduced, thereby providing a corresponding reduction in power consumption and heat dissipation of the selected portions of the circuit. The use of the array of parallel in, parallel out registers (as opposed to the serial register used in contemporary devices) for pattern detection and data selection facilitates such reduced clock rates.
Thus, according to the preferred embodiment of the present invention, the first clock signal comprises an approximately 1 GHz clock signal for facilitating reception of asynchronous data by the serial in, parallel out register at approximately 1 GHz; the second clock signal comprises an approximately 500 MHz clock signal for facilitating identification of the delimiter character as data moves through the array of parallel in, parallel out registers; and the third clock signal comprises an approximately 100 MHz clock signal for facilitating generation of 10-bit, clock aligned, framed parallel output words at approximately 100 MHz.
The multi-frequency clock preferably further comprises a clock recovery circuit for facilitating generation of the first, second, and third clock signals from the asynchronous serial data. The clock recovery circuit preferably comprises a phase lock loop clock recovery circuit which generates or regenerates an asynchronous timing reference signal from a serial data stream and provides a timing reference to mark in time the anticipated occurrence of serial data bits. In effect, the phase-lock loop generates a synchronous stream of successive timing references, each timing reference representing, for example, a bit period with which a data bit may be associated.
According to the preferred embodiment of the present invention, the serial in, parallel out register has a smaller bit size than the bit size of the clock aligned, framed parallel output word. Preferably, the serial in, parallel out register comprises a 5-bit register and the framed output word comprises a 10-bit output word.
The serial in, parallel out register preferably comprises a serial in, parallel out shift register and the array of parallel in, parallel out register preferably comprise an array of parallel in, parallel out shift registers. The array of parallel in, parallel out shift registers preferably comprise four 5-bit parallel in, parallel out shift registers and a single 1-bit register.
The pattern detection circuit is preferably configured to detect a 10-bit delimiter word. More particularly, the pattern detection circuit is preferably configured to detect a 7-bit delimiter character contained within a 10-bit word which also contains 3 don""t care bits.
Because the location of the starting bit of the delimiter character is unknown when the delimiter character is received within the serial in, parallel out register, it is necessary to locate the delimiter character as the delimiter character progresses through the array of parallel in, parallel out registers. Since a 5-bit serial in, parallel out register is utilized according to the preferred embodiment of the present invention, the delimiter character may be located at one of five different starting positions within the array of parallel in, parallel out registers. Thus, the pattern detection circuit is configured to detect the delimiter character when the delimiter character is located at one of the five different starting positions within the array of parallel in, parallel out registers.
According to the preferred embodiment of the present invention, the selection circuit comprises a plurality of multiplexers configured to select a desired sequence of bits from within the array of parallel in, parallel out registers and to provide an output representative of the selected bits. The selection circuit preferably comprises a first multiplexer array configured to select one of two different sequences of bits within the array of parallel in, parallel out registers, so as to provide a first selection which comprises the delimiter character as well as some superfluous bits. The selection circuit also comprises a second multiplexer array configured to select a desired sequence of bits from within the first selection so as to provide a second selection. The second selection defines the framed parallel output word.
According to the preferred embodiment of the present invention, the selection circuit comprises fourteen 2:1 multiplexers configured to select one of two different sequences of 14 bits within the array of parallel in, parallel out registers to provide a 14-bit first selection and comprises ten 5:1 multiplexers configured to select one of five different sequences of 10-bits within the first selection so as to provide a 10-bit second selection which defines the framed parallel output word.
Since the desired 10-bit word is moving through the array of parallel in, parallel out registers, it will pass through both of the 14-bit sequences of registers which potentially comprises the first selection. The two 14-bit selections are 5 nanoseconds apart within the array. Thus, the 14-bit sequence selected is that sequence which enhances alignment of the desired 10-bit data word with the desired clock signal.
According to the preferred embodiment of the present invention, the data alignment circuit comprises a delay register for receiving the framed parallel output word from the selection circuit and an output multiplexer for selecting the framed parallel output word from either the selection circuit or the delay register. The output multiplexer selects the framed parallel output word which enhances alignment of the framed parallel output word with a desired clock signal. Thus, the output multiplexer selects the framed parallel output word directly from the selection circuit if no delay is needed to enhance alignment of the framed parallel output word with the desired clock signal. The output multiplexer selects the framed output word from the delay register if the delay provided thereby enhances alignment of the framed parallel output word with the desired clock signal. The output multiplexer provides a substantially clock aligned, framed, parallel output word.
According to the preferred embodiment of the present invention, the data alignment circuit comprises a 10-bit parallel in, parallel out delay register for receiving the framed, parallel output word from the selection circuit and ten 2:1 output multiplexers for selecting the framed parallel output word from either the selection circuit or the delay register. The ten 2:1 output multiplexers select the frame parallel output word in a manner which further enhances alignment of the framed parallel output word with the desired clock signal. A ten nanosecond timing difference is provided between the output of the ten 2:1 multiplexers and the delay register. Thus, the ten 2:1 output multiplexers provide a substantially clock aligned, framed parallel output word.
An output register receives the course clock aligned, framed parallel output word from the output multiplexer. The output register further aligns the substantially clock aligned, framed parallel output word to the desired clock signal so as to provide a clock aligned, framed parallel output word. According to the preferred embodiment of the present invention, the output register comprises a 10-bit output register.
Thus, the present invention provides a high speed serial to parallel data converter suitable for use in a Fibre Channel receiver. The serial to parallel converter uses less power than contemporary serial to parallel data converters and is thus more suitable than contemporary serial to parallel data converters for implementation as an integrated circuit.